The present invention relates to soft-start techniques for control loops that regulate DC/DC converters, and in particular, soft-start circuits and methods that control the output of an error amplifier in response to a ramp signal and a switching frequency of the DC/DC converter.
A DC/DC converter is a circuit that provides output current to a load at a regulated output voltage VO in response to a unregulated input voltage VIN. DC/DC converters are well known to those of skill in the art. A typical DC/DC converter design is shown in FIG. 1.
DC/DC converter 101 provides current from VIN to the load through two synchronously operated switches. Output inductor Lo smoothes the output current, and output capacitor Co smoothes the output voltage. DC/DC converter 101 is referred to as a buck converter, because it steps down VIN to a lower voltage VO.
Error Amplifier 102 receives a feedback signal VFB from the output voltage VO and generates an error signal VERROR at the input of PWM comparator 103. Pulse width modulation (PWM) is a commonly employed circuit technique in the control loop of a DC/DC converter. Comparator 103 receives VERROR at its non-inverting input and a ramp voltage VRAMP at its inverting input. Comparator 103 transforms VERROR into a duty cycle for the two switches in DC/DC converter 101.
During the power-on phase of converter 101, the output voltage of error amplifier 102 is clamped and released gradually to allow the duty cycle of the DC/DC converter switches to increase slowly from zero. Error amplifier 102 has a soft-start clamp circuit that performs this function during power-on. Soft-start clamp circuitry prevents inrush current into the empty output capacitor.
FIG. 2 illustrates an example of a conventional soft-start clamp circuit 202 that is coupled to an error amplifier 201 in a DC/DC converter. An example of an error amplifier 201 is also shown in FIG. 2. Soft-start clamp circuit 202 includes a constant current source 210 and a capacitor 211. Circuit 202 generates a very slow-sloped ramp voltage VSS that clamps the output voltage VERROR of error amplifier 201.
There are a number of problems with the soft-start clamp circuit shown in FIG. 2. One potential problem relates to the voltage range of voltage VSS. If the voltage range of voltage VSS is far beyond the voltage range of the ramp voltage VRAMP, circuit 202 does not provide an effective soft-start function that controls the duty cycle of the switches to prevent inrush current into output capacitor Co.
For example, VRAMP has a voltage amplitude of 1 volt in FIG. 1. The 1 volt amplitude may, for example, exist over a range from 2 volts to 3 volts. On the other hand, the range of VSS starts from 0 volts and increases to a maximum value of the supply voltage VDD (e.g., 5 volts) in FIG. 2.
Soft-start circuit 202 does not begin to control the duty cycle of the switches in converter 101, until capacitor 211 has been charged from 0 volts to 2 volts. Once capacitor 211 has been charged to 3 volts, the maximum duty cycle (100%) of the switches is reached, and soft-start circuit 202 no longer reduces the duty cycle of the switches.
Thus, soft-start circuit 202 does not correlate VSS with the amplitude of VRAMP. Also, soft-start circuit 202 does not correlate VSS with switching frequency of the switches in converter 101.
FIG. 3 illustrates another prior art control loop for a DC/DC converter 101. The control loop of FIG. 3 was implemented for high speed central processing unit (CPU) applications. The control loop of FIG. 3 employs a low gain, wide bandwidth error amplifier 301 with summing mode and droop control. Error amplifier 301 amplifies the difference between feedback voltage VFB and a reference voltage VD. VD is a target output voltage for VO. VD is generated by a digital-to-analog converter. The numbers over the resistors represent resistance values in kilo-ohms.
The control loop of FIG. 3 also has a unity gain buffer 302 and a PWM comparator 303. Comparator 303 compares ramp voltage VRAMP with the output of buffer 302 and a current feedback signal IFB. The current feedback signal IFB is a function of the instantaneous inductor current IL and the current gain G of the inductor Lo.
In the control loop of FIG. 3, a technique referred to as feed-forward compensation (FFC) is employed. According to this technique, voltage VRAMP is a function of both the input voltage VIN and the target output voltage VD.
The valley voltage of VRAMP in FIG. 3 equals 3 volts−(K×VD), where VD is the target output voltage. K equals 1−(1/VIN). The peak-to-peak amplitude of VRAMP is a constant value of 1 volt. Thus, voltage VRAMP is adjusted along with the input voltage VIN and the target output voltage.
In the control loop of FIG. 3, the conventional soft-start control circuit 202 is also not effective, because the soft-start voltage VSS is independent of the amplitude of VRAMP and the switching frequency of the switches.
Therefore, there is a need for an improved soft-start implementation that is capable of tracking variations in the operational parameters of a control loop such as the amplitude of the ramp voltage and the switching frequency of the switches in a DC/DC converter.